/PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a planet leader in software and IP for semiconductor blueprint, authentication and producing, this day announced the instant accessibility of the DesignWare® DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. The DesignWare DDR PHY compiler proffers designing managers a web-based User Interface to gather a modified, high-performance DDR PHY for their system-on-chips (SoCs). The DesignWare DDR PHY compiler assesses more than Sixty variables and permits the appraisal of infinite ‘what-if’ scenarios. The output of the PHY compiler is a modified tough DDR PHY that is perfected for the aim application.


“As a leading fabless blueprint integrator, GUC is committed to supplying fine quality makes to our buyers,” said Dr. Keh-Ching Huang


, head of Promotion and IP Solution Planning at Worldwide UniChip. “Synopsys’ DesignWare DDR PHY compiler has assisted us resolve what has usually been an extremely complicated and time taking objective. We’ve applied the compiler to refine the DesignWare DDR PHY to reach our perfect PHY realization, saving us considerable time and effort.”


Supporting the DesignWare DDR2/3-Lite, DDR 3/2 and DDR multiPHY IP goods, the DesignWare DDR PHY compiler’s User Interface steps the individual through a series of conclusions as they create their DDR PHY from tough IP constituents, incorporating application-particular DDR I/Os. Designing Managers have control over numerous variables incorporating supported DRAM types (like DDR3, DDR2, Mobile DDR and/or LPDDR2), foundry and process node, memory channel breadth, power-to-signal ratios, core power necessities and different physical placement variables. The DesignWare DDR PHY compiler makes a promptly observable image of the DDR PHY outline, a list of the pins, area, a power intake report, placement scripts and an RTL model of the PHY.


“The DDR interface is an essential element of most SoCs, specifically the I/O ring, which might considerably effect the die size and power of the blueprint,” said John Koeter


, vice president of promotion for the Solutions Group at Synopsys. “Synopsys developed the DesignWare DDR PHY compiler to address our buyers’ need for application-particular DDR PHYs that meet their belligerent power and area necessities.”


Synopsys’ all-inclusive DesignWare DDR IP offering incorporates digital regulators and PHY IP


supporting DDR, DDR2, DDR3, Mobile DDR and LPDDR2. The DesignWare DDR PHY IP supports leading process technologies and incorporates a DFI 2.1-agreeable interface. Synopsys’ DesignWare International DDR Memory and Protocol Regulator IP complement the DesignWare DDR PHY IP, offering an all-inclusive DDR interface solution from a single IP vendor. Synopsys assists lower incorporation risk by supplying fine quality DDR IP solutions that have been used in hundreds of applications and are shipping in volume production.


Synopsys will be exhibiting the DesignWare DDR PHY compiler at the forthcoming DesignCon 2011 Meeting (compartment number 606) on February Two-Three


at the Santa Clara


Convention Center in Santa Clara, California


.


Accessibility


The DesignWare DDR PHY compiler is on hand to approved buyers of select DesignWare DDR PHY IP this day. For access to the DesignWare DDR PHY compiler as part of the Synopsys “Attempt the PHY” program, visit: https://www.synopsys.com/dw/ddrphy.php


About DesignWare IP


Synopsys is a leading supplier of fine quality, silicon-attested IP solutions for SoC makes. The extensive DesignWare IP portfolio incorporates complete interface IP solutions incorporating regulators, PHY and Authentication IP for well known protocols, analog IP, embedded memories, logic libraries, embedded test & overhaul IP, audio post-processing software and configurable processor cores. Additionally, Synopsys proffers SystemC transaction-level models to make virtual prototypes for quick, pre-silicon development of software. With a strong IP development methodology, reuse instruments, all-embracing investment in quality and all-inclusive tech support, Synopsys allows designing managers to speed up time-to-market and decrease incorporation risk. For more data on DesignWare IP, visit: http://www.synopsys.com/designware. Follow us on Twitter at http://twitter.com/designwareip.


About Synopsys


Synopsys, Inc. (Nasdaq: SNPS) is a planet leader in electronic blueprint automation (EDA), providing the worldwide electronics market with the software, intellectual property (IP) and services utilized in semiconductor blueprint, authentication and producing. Synopsys’ all-inclusive, incorporated portfolio of realization, authentication, IP, producing and area-programmable gate array (FPGA) solutions assists address the key challenges designing managers and producers face this day, like power and gain management, system-to-silicon authentication and time-to-results. These tech-leading solutions help give Synopsys buyers a competitive edge in taking the perfect goods to market fast while decreasing costs and plan risk. Synopsys is headquartered in Hill View, California


, and has roughly Seventy offices located all the way through United States And Canada


, Europe


, Japan


, Asia


and India


. Visit Synopsys on-line at http://www.synopsys.com/.


Synopsys and DesignWare are registered brands of Synopsys, Inc. Any other brands or maybe registered brands noted in that release are the intellectual property of their corresponding holders.


SOURCE Synopsys, Inc.


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